发明名称 MULTIPLE LENGTH DATA SUM OF PRODUCT ARITHMETIC PROCESSING CIRCUIT AND MONTGOMERY PRODUCT SUM REMAINDER ARITHMETIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a multiple length data sum of product arithmetic processing circuit which is capable of efficiently perform sum of product arithmetics even in the case of use of a single port memory. SOLUTION: A MAC 23 performs sum of product arithmetic processing with a multiplier and a multiplicand different in bit width, and registers 13, 14, 15, 16, 17 adjust the data volumes to be supplied to the MAC 12 in a one-clock time, of multiple length data in accordance with bit width thereof so that the sum total of the consumption data volume and the generated data volume in the one-clock time in the MAC 12 may be the data volume which can be transferred in the one-clock time in a memory 11. Thus the circuit use efficiency of the MAC 12 is not reduced even when the single port memory 11 has a data transfer capability. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005209095(A) 申请公布日期 2005.08.04
申请号 JP20040017205 申请日期 2004.01.26
申请人 FUJITSU LTD 发明人 MUKODA KENJI;TAKENAKA MASAHIKO;TORII NAOYA;MASUI SHOICHI
分类号 G06F7/52;G06F7/544;G06F7/72;G09C1/00;(IPC1-7):G06F7/72 主分类号 G06F7/52
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