发明名称 STORING INSTRUCTIONS IN LOW POWER SHIFT REGISTER BUFFER FOR FETCHING LOOP INSTRUCTIONS
摘要 A controller for a digital processor includes a power consuming random access memory (12) storing instructions. To reduce power consumption when loop instructions are processed, the loop instructions are stored in a shift register (24), when the instructions are first fetched from the memory for execution. A memory controller (20) including a state tracking machine (210) monitors the execution (16) of the instructions and determines when a loop has been entered, whereupon instructions are fetched from the shift register instead of the memory until the loop is exited. The process is initiated for each loop in a nested loops. The controller does not require a special instruction either preceding or following a loop.
申请公布号 WO9960460(A3) 申请公布日期 2000.02.10
申请号 WO1999US11280 申请日期 1999.05.21
申请人 TELLABS OPERATIONS, INC. 发明人
分类号 G06F9/32;G06T1/20 主分类号 G06F9/32
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