PLANER TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THE SAME

摘要

A planer type semiconductor device and a method for manufacturing the same are provided to improve the reliability of breakdown voltage by using partial non-silicidation of a drain edge of a gate-poly. An oxide layer is formed on a semiconductor substrate(100) including a well region(120). An STI(140) is performed on the semiconductor substrate and the oxide layer. One or more drift region(150) is formed by implanting dopants into one side or both sides of the well region. A gate pattern is formed by forming and patterning a gate oxide layer and a polysilicon layer on the oxide layer. A source region(161,162) and a drain region(160) are formed by implanting dopants into the semiconductor substrate of both sides of the gate pattern. A silicide prevention mask is formed on the drift region including one side of the polysilicon layer of the gate pattern. A silicide process using the silicide prevention mask is performed.