BIT LINE DUMMY CORE-CELL AND METHOD FOR PRODUCING SAME

摘要

PROBLEM TO BE SOLVED: To provide a dummy core cell obtaining an optimum self-timing signal.

SOLUTION: The bit line dummy core-cell includes a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled to form a bi-stable flip-flop. The first inverter including a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter includes a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second DMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node can always store a high level logical value.

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