发明名称 |
APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE |
摘要 |
Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row. |
申请公布号 |
US2016203865(A1) |
申请公布日期 |
2016.07.14 |
申请号 |
US201314913676 |
申请日期 |
2013.09.27 |
申请人 |
INTEL CORPORATION |
发明人 |
MANIPATRUNI SASIKANTH;NIKONOV DMITRI E.;YOUNG IAN A. |
分类号 |
G11C13/00 |
主分类号 |
G11C13/00 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. |
地址 |
Santa Clara CA US |