SEMICONDUCTOR DEVICE

摘要

A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.

主权项

1. A semiconductor circuit comprising:
a first circuit that determines a voltage of a first node in response to an input data signal and a clock signal; a first latch that determines a voltage of a second node in response to the voltage of the first node and the clock signal; a second latch that determines a voltage of a third node in response to the voltage of the second node and the clock signal; and a second circuit that provides an output data signal in response to the voltage of the third node and the clock signal, wherein the first circuit comprises:
a first transistor of first type (P1) connected to a power supply voltage and gated by the input data signal;a first transistor of second type (N1) connected between ground and the first node and gated by the input data signal; anda second transistor of first type (P2) connected between P1 and the first node and gated by the clock signal to control the output of P1 with respect to the first node; and the first latch comprises:
a fourth transistor of first type (P4) gated by the voltage of the first node and pulling up the voltage of the second node;a fifth transistor of first type (P5) connected between the power supply voltage and P4 and gated by the clock signal;a fourth transistor of second type (N4) connected in series with P4, gated by the voltage of the first node, and pulling down the voltage of the second node; anda third transistor of second type (N3) connected between N4 and ground and gated by the clock signal.