Hardware Delay Compensation in Digital Phase Locked Loop

摘要

In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

主权项

1. A digital phase locked loop (PLL) comprising:
a PLL loop comprising:
a first phase sampler for sampling a reference signal to generate a reference signal phase value,a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to the reference input signal,a first phase comparator for comparing said reference signal phase value with a feedback phase value derived from said PLL loop to generate a phase error value, anda loop filter for filtering said error phase value to derive said control value; a hardware-implemented controlled oscillator responsive to output phase and frequency value from said first SDCO to synthesize clock signals, said synthesized clock signals, or derivatives thereof, being subject to a hardware delay; and a hardware delay compensation loop including a second phase sampler for sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock signal phase values, a second phase comparator for comparing said synthesized clock signal phase values with feedback phase values derived from said PLL loop to generate a compensation value to modify said synthesized clock signals or derivatives thereof to compensate for said hardware delay.