| 摘要 |
PROBLEM TO BE SOLVED: To realize improvement in the parallelism of SIMD processing and increase in the degree of freedom of non-SIMD processing while suppressing increase in hardware scale.SOLUTION: An arithmetic processing unit comprises: a plurality of or three or more computing elements processing single data individually or processing a plurality of pieces of data in parallel; a plurality of storage destination register groups provided to correspond to the computing elements, respectively; a plurality of renaming register groups; and a register naming unit, a register set including the storage destination register groups and the renaming register groups include not only a basic register set used for computing in response to a multiple-data instruction and computing in response to a non-multiple-data instruction but also a first extension register set used for computing in response to the multiple-data instruction and computing in response to the non-multiple-data instruction and a second extension register set used for computing in response to the multiple-data instruction but not used for computing in response to the non-multiple-data instruction, and the register renaming unit stores a correspondence in the basic register set and a correspondence in the first extension register set. |
