| 摘要 |
A network-on-chip apparatus and a method for controlling a dynamic frequency of the same are provided to prevent a deadlock in a network system by lowering an operation frequency of a processing element. A network-on-chip apparatus includes a plurality of network interfaces, a network, and a plurality of bidirectional links. The network interface includes an output packet buffer(912), an input packet buffer(914), a packet composer and decomposer(911), and an automatic clock control unit(916). The output packet buffer outputs sequentially stored packets to a corresponding switch via a link connected to an output packet port. The input packet buffer sequentially stores a packet received from a switch via an input packet port. The packet composer and decomposer composes a packet using an address signal, a control signal, and a data signal received from processing elements(100), stores the composed packet in the output packet buffer, decomposes a packet provided from the input packet buffer, decrypts the decomposed packet, and delivers the decrypted packet to the processing element. The automatic clock control unit controls a clock frequency outputted to a corresponding processing element according to a backlog of the output packet buffer.
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