发明名称 |
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a technology for reducing a shortage between a selective gate electrode and a memory gate electrode in a semiconductor device having a MONOS type non-volatile memory cell of a split gate structure. SOLUTION: It is possible to prevent the formation of a silicide layer 3 crossing over a wall constituted of insulating films 6b, 6t and an electric charge storage layer CSL even if the silicide layer 3 formed by a self-align method is formed on the upper surface of the selective gate electrode CG and the upper surface of the memory gate electrode MG by etching the upper surface of first polycrystalline silicon constituting the selective gate electrode CG and the upper surface of second polycrystalline silicon constituting a memory gate electrode MG and forming between the selective gate electrode CG and the memory gate electrode MG a wall which is higher than upper surfaces of the electrodes by 10-20 nm and which is constituted of the insulating films 6b and 6t and the charge storage layer CSL. COPYRIGHT: (C)2008,JPO&INPIT
|
申请公布号 |
JP2008211016(A) |
申请公布日期 |
2008.09.11 |
申请号 |
JP20070046836 |
申请日期 |
2007.02.27 |
申请人 |
RENESAS TECHNOLOGY CORP |
发明人 |
MORIYAMA TAKUJI;MATSUI SHUNICHI |
分类号 |
H01L21/8247;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
H01L21/8247 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|