发明名称 半導体回路パターン計測装置及び方法
摘要 Included is a multiple resolution image generating unit which applies a plurality of noise removing filters to a semiconductor circuit pattern image and generates a multiple resolution image, a multiple resolution differential image generating unit which generates a multiple resolution differential image from a difference of images between hierarchies of the multiple resolution image, and a contour extracting unit which extracts a contour of the semiconductor circuit pattern based on an intensity signal of the semiconductor circuit pattern image. The contour extracting unit calculates an intensity signal level upon extracting a contour of the semiconductor circuit pattern from the multiple resolution image by using an image signal of the multiple resolution differential image, and extracts a contour of the semiconductor circuit pattern based on the calculated intensity signal level.
申请公布号 JP5810031(B2) 申请公布日期 2015.11.11
申请号 JP20120102042 申请日期 2012.04.27
申请人 株式会社日立ハイテクノロジーズ 发明人 柴原 ▲琢▼磨;及川 道雄;酒井 計;山口 聡
分类号 G06T7/60;G06T1/00 主分类号 G06T7/60
代理机构 代理人
主权项
地址