发明名称 |
MEMORY UNIT WITH VOLTAGE PASSING DEVICE |
摘要 |
A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal. |
申请公布号 |
US2016293261(A1) |
申请公布日期 |
2016.10.06 |
申请号 |
US201615065878 |
申请日期 |
2016.03.10 |
申请人 |
eMemory Technology Inc. |
发明人 |
Chen Chih-Hsin;Wang Shih-Chen;Lai Tsung-Mu |
分类号 |
G11C16/14;G11C16/10 |
主分类号 |
G11C16/14 |
代理机构 |
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代理人 |
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主权项 |
1. A memory unit, comprising:
a first voltage passing device configured to output voltages according to operations of the memory unit; and a first memory cell comprising:
a first floating gate transistor having a first terminal configured to receive a first bit line signal, a second terminal, and a floating gate; anda first capacitance element having a first terminal coupled to the first voltage passing device, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a body configured to receive a first control signal; wherein: the first capacitance element and the first voltage passing device are disposed in a first N-well; the first terminal of the first capacitance element receives a first voltage outputted from the first voltage passing device during a program operation or an erase operation of the first memory cell and receives a second voltage outputted from the first voltage passing device during an inhibit operation of the first memory cell; and the first voltage is greater than the second voltage. |
地址 |
Hsin-Chu TW |