NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING

摘要

A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.

主权项

1. A memory, comprising:
a plurality of non-volatile memory devices, each comprising a plurality of nonvolatile memory cells; a write controller configured to stream bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that optimize a speed of writing to the memory devices to provide writes at a first speed, wherein consecutive groups of bits are written to consecutive memory cells within respective memory devices; a self-referenced read controller configured to read bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for speed or latency of data transmission to provide reads at a second speed that is slower than the first speed; and a bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.