发明名称 CACHE AND DATA ORGANIZATION FOR MEMORY PROTECTION
摘要 This disclosure is directed to cache and data organization for memory protection. Memory protection operations in a device may be expedited by organizing cache and/or data structure while providing memory protection for encrypted data. An example device may comprise processing module and a memory module. The processing module may include a memory encryption engine (MEE) to decrypt encrypted data loaded from the memory module, or to encrypt plaintext data prior to storage in the memory module, using security metadata also stored in the memory module. Example security metadata may include version (VER) data, memory authentication code (MAC) data and counter data. Consistent with the present disclosure, a cache associated with the MEE may be partitioned to separate the VER and MAC data from counter data. Data organization may comprise including the VER and MAC data corresponding to particular data in the same data line.
申请公布号 US2016275018(A1) 申请公布日期 2016.09.22
申请号 US201514661044 申请日期 2015.03.18
申请人 Intel Corporation 发明人 CHHABRA SIDDHARTHA;MAKARAM RAGHUNANDAN;MCCORMICK JIM;BHATTACHARYYA BINATA
分类号 G06F12/14;G06F12/08 主分类号 G06F12/14
代理机构 代理人
主权项 1. A device including memory protection, comprising: memory circuitry; and processing circuitry including at least: a memory encryption engine to at least one of decrypt encrypted data loaded from the memory circuitry using security metadata loaded from the memory circuitry, or encrypt plaintext data prior to storage in the memory circuitry by traversing levels of a counter tree using the security metadata, the memory encryption engine including at least a partitioned cache to hold the security metadata.
地址 Santa Clara CA US