发明名称 |
DIGITALLY PHASE LOCKED LOW DROPOUT REGULATOR |
摘要 |
Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference. |
申请公布号 |
EP2901235(A4) |
申请公布日期 |
2016.09.28 |
申请号 |
EP20120885472 |
申请日期 |
2012.09.25 |
申请人 |
INTEL CORPORATION |
发明人 |
RAYCHOWDHURY, ARIJIT;SOMASEKHAR, DINESH;TSCHANZ, JAMES W.;DE, VIVEK K. |
分类号 |
G05F1/56 |
主分类号 |
G05F1/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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