发明名称 Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency
摘要 A method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge includes a bus activity monitor for monitoring bus cycles on a first bus, an inbound posting buffer, and a control logic. The control logic indicates whether to grant control of the first bus to a first processor on the first bus based on whether the inbound posting buffer is empty, and also controls disabling of posting to the inbound posting buffer. The control logic disables inbound posting responsive to both the first processor being backed off the system bus a predetermined number of times and the inbound posting buffer being empty.
申请公布号 US6026460(A) 申请公布日期 2000.02.15
申请号 US19960644180 申请日期 1996.05.10
申请人 INTEL CORPORATION 发明人 DAVID, HOWARD S.;MCTAGUE, MICHAEL J.
分类号 G04F13/00;(IPC1-7):G04F13/00 主分类号 G04F13/00
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