| 摘要 |
A nonvolatile memory in which transistors having MFMIS structure each of which is composed by sequentially laminating a floating-gate, a ferroelectric layer and a control gate via a gate insulating film on the surface of a semiconductor substrate between a source area and a drain area formed on the semiconductor substrate are arrayed in a matrix, wherein the control gate is connected to a word line, said source area is connected to a source line and said drain area is connected to a drain line; a floating line composed of writing gates composed so that a capacitor is formed between the writing gate and said floating-gate is provided; a word line and a source line on the same line in said matrix are connected in common;a drain line and a floating line in the same column in said matrix are connected in common; and source/drain voltage and gate voltage can be independently set.
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