发明名称 |
RANDOMIZED MODULAR POLYNOMIAL REDUCTION METHOD AND HARDWARE THEREFOR |
摘要 |
<p>A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates (32) and randomizes (36) a polynomial quotient q' (x) used for computation of a polynomial remainder. The randomizing error E (x) injected into the approximate polynomial quotient q (x) is limited to a few bits, e.g. less than half a word. The computed (38) polynomial remainder r' (x) is congruent with but a small random multiple of the residue r (x), which can be found by a final strict binary field reduction by the modulus M (x). In addition to a computational unit (10) and operations sequencer (16), the computing hardware also includes a random or pseudo-random number generator (20) for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks.</p> |
申请公布号 |
WO2006124160(A3) |
申请公布日期 |
2007.12.13 |
申请号 |
WO2006US13795 |
申请日期 |
2006.04.12 |
申请人 |
ATMEL CORPORATION;DUPAQUIS, VINCENT;DOUGUET, MICHEL |
发明人 |
DUPAQUIS, VINCENT;DOUGUET, MICHEL |
分类号 |
H04L9/00 |
主分类号 |
H04L9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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