SYNTHESIS OF REDUCED NETLIST HAVING POSITIVE ELEMENTS AND NO CONTROLLED SOURCES

摘要

In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist.

主权项

1. A circuit analysis method comprising:
obtaining a netlist of a circuit; generating a reduced model from the netlist; using the reduced model to synthesize a positive netlist having no controlled current or voltage sources; and unstamping the synthesized positive netlist.