SYSTEM-ON-CHIP HAVING IEEE 1500 WRAPPER AND INTERNAL DELAY TEST METHOD THEREOF

摘要

A system-on-chip having IEEE 1500 wrapper and an internal delay test method thereof are provided to reduce the number of test pins by using a TAP controller. An IEEE 1500 wrapped core(230) comprises a core(2390) having a scan-chain(2391). The IEEE 1500 wrapper(2310~2380) provides an interface between a TAP controller and the core. A wrapper instruction register(2310) determines the action mode corresponding to the wrapper control signal(WSC) set. A wrapper bypass register(2320) is selectively operated by the wrapper instruction register. A WSC-WBC decoder(2330) converts the wrapper control signal into the test control signal for performing the test operation according to the invention. A multiplexer controller(2340) produces control signals controlling input-output wrapper border cells. A boundary test clock generator(2350) produces the input-output clock of wrapper border cells. A scan test clock generator(2360) produces the core scan-chain test clock(STCLK).