发明名称 SUB-MODULE PHYSICAL REFINEMENT FLOW
摘要 A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow.
申请公布号 US2015379165(A1) 申请公布日期 2015.12.31
申请号 US201514852875 申请日期 2015.09.14
申请人 Synopsys, Inc. 发明人 KNAPP Kevin
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method for designing electronic circuit each having a plurality of sub-circuits, the method comprising: receiving, at one or more computer systems, a circuit design having a plurality of sub-modules, the information including at least a circuit connectivity description, logical constraints, and physical constraints for at least one of the plurality of sub-modules; receiving, at the one or more computer systems, information indicative of a change to the at least one of the plurality of sub-modules of the circuit design; determining, with one or more processors associated with the one or more computer systems, how the at least one sub-module interfaces with the circuit design based on the circuit connectivity description, logical constraints, and physical constraints; determining, with one or more processors associated with the one or more computer systems, how the at least one sub-module may be placed within the circuit design based on the circuit connectivity description, logical constraints, and physical constraints; and generating, with the one or more processors associated with the one or more computer systems, information configured to integrate the changed at least one sub-module into the circuit design based on a determination of how the at least one sub-module interfaces with the circuit design and a determination of how the at least one sub-module may be placed within the circuit design.
地址 Mountain View CA US