发明名称 Circuit Arrangement and Method for the Provision of a Clock Signal with an Adjustable Duty Cycle
摘要 The circuit arrangement (1) comprises an input (2) for the connection of an oscillator (3) and an amplifier circuit (20) having a first input (21) that is coupled to the input (1) of the circuit arrangement (1), having a second input (22) and an output (23) that is connected to an output (4) of the circuit arrangement (1). A clock signal (Vout) with a duty cycle (phi) can be accessed at the output (4) of the circuit arrangement (1) The circuit arrangement (1) furthermore incorporates a low-pass filter (40), the input of which is connected to the output (23) of the amplifier circuit (20), and an integrator circuit (50) the input of which is connected to the low-pass filter (40) and the output of which is connected to the second input (22) of the amplifier circuit (20) for the delivery of an adjustable threshold value (Vth) for controlling the duty cycle (phi).
申请公布号 US2009072873(A1) 申请公布日期 2009.03.19
申请号 US20080210752 申请日期 2008.09.15
申请人 AUSTRIAMICROSYSTEMS AG 发明人 DENIER URS
分类号 H03K3/017 主分类号 H03K3/017
代理机构 代理人
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