MISFET Device

摘要

Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode.

主权项

1. A metal-insulator-semiconductor field effect transistor (MISFET) device, comprising:
a barrier layer on a substrate; a source/drain over and in direct contact with the barrier layer; a first etch stop layer on the source/drain; a gate dielectric layer on the substrate, a portion of the gate dielectric layer overlapping a portion of the first etch stop layer; a gate electrode on the gate dielectric layer; a second etch stop layer on the gate electrode; an inter-layer dielectric over the substrate, the source/drain, and the gate electrode; a first contact extending through the inter-layer dielectric and the first etch stop layer to the source/drain; and a second contact extending through the inter-layer dielectric and the second etch stop layer to the gate electrode.