Stress memorization techniques for transistor devices

摘要

One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.

主权项

1. A method of forming a transistor device comprising a gate structure and a plurality of source/drain regions, the method comprising:
performing a source/drain extension ion implantation process with a dopant material to thereby form a doped extension implant region in said source/drain regions; performing a Group VII material ion implantation process on said source/drain regions with a Group VII material; after performing said Group VII material ion implantation process, forming a capping material layer above said source/drain regions; with said capping material layer in position, performing an anneal process so as to form stacking faults in said source/drain regions; removing said capping material layer; forming epi semiconductor material for said source/drain regions after removing said capping material layer; performing a deep source/drain ion implantation process with a dopant material after forming said epi semiconductor material; and performing a second anneal process to activate implanted dopant materials from said deep source/drain ion implantation process.