| 摘要 |
A low capacitance chip device and a method for manufacturing the same are provided to minimize a floating capacitance caused by an external electrode by minimizing a contact area with the external electrode. A low capacitance chip device includes a laminated body, first external electrode(36) and second external electrode(38). A first ceramic layer, a first internal electrode(26) and a second internal electrode(30) are formed on the laminated body. A second ceramic layer, having a higher dielectric rate than the first ceramic layer, is laminated on the laminated body using as reactive limitation layer as a medium material. The first and second external electrodes are formed on both sides of the laminated body. The first external electrode is contacted with an end of the first internal electrode. The second external electrode is contacted with an end of the second internal electrode.
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