摘要 |
A finite field inverse circuit has a finite field data unit (1112) and an inverse control unit (1110). The inverse control unit includes (1110) a kl and ku decrementer pair (1108, 1122), a kl-ku difference unit (1106), an inverse control finite state machine (1102), and a one-bit memory (1104) coupled to the inverse control finite state machine (1102). The finite field data unit (1112) includes four m bit wide registers that are shift registers designated as B (1120), A (1118), M (1114), and C (1116), where B- is a first register, A- is a second register, M- is a irreducible polynomial register, and C- is a field element register. An the irreducible polynomial is loaded left justified in the M-register, a field element to be inverted is loaded left justified in the C-register, and a single "1" is loaded in an LSB bit of the B-register. The field element is then inverted in 2n+2 system clock cycles where n is a field size associated with the field element.
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申请人 |
MOTOROLA, INC.;CERTICOM CORP. |
发明人 |
DWORKIN, JAMES DOUGLAS;GLASER, P. MICHAEL;TORLA, MICHAEL JOHN;VADEKAR, ASHOK;LAMBERT, ROBERT JOHN;VANSTONE, SCOTT ALEXANDER |