Optical driver including a multiphase clock generator having a delay locked loop (DLL), optimized for Gigahertz frequencies

摘要

A delay locked loop (DLL) circuit comprising a first series of M first delay cells disposed in a feedback loop, each first delay cell providing a delay of N D, wherein N is an odd integer and D is controlled by a control voltage; and a second series of M second delay cells, each having a delay of N D, for generating M clocks having M different phases respectively based on an input clock.