发明名称 インターコネクト内の低減されたレイテンシのバリアトランザクション要求
摘要 Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.
申请公布号 JP5865976(B2) 申请公布日期 2016.02.17
申请号 JP20140186541 申请日期 2014.09.12
申请人 エイアールエム リミテッド 发明人 リオクリュクス、ピーター、アンドリュー;マシューソン、ブルース、ジェイムズ;レイコック、クリストファー、ウィリアム;グリセンスウェイト、リチャード、ロイ
分类号 G06F15/173 主分类号 G06F15/173
代理机构 代理人
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