发明名称 System and method for determining on-chip bit error rate (BER) in a communication system
摘要 <p>A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received. Accordingly, the bit error rate may be calculated based on a ratio of the number of counted bits in error to the number bits counted in the at least a portion of the number of bits received. </p>
申请公布号 EP1388969(A3) 申请公布日期 2007.09.19
申请号 EP20030018065 申请日期 2003.08.07
申请人 BROADCOM CORPORATION 发明人 FAN, NONG;HOANG, TUAN;JIANG, HONGTAO
分类号 H04L1/24;H04L1/20 主分类号 H04L1/24
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