TECHNIQUES FOR PROGRAMMING OF SELECT GATES IN NAND MEMORY

摘要

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

主权项

1. A memory structure, comprising:
a plurality of serially-connected drain select transistors; a plurality of memory transistors coupled to the plurality of serially-connected drain select transistors; and one or more source select transistors coupled to the plurality of memory transistors, wherein the plurality of serially-connected drain select transistors comprises a first drain select transistor coupled to a bit line and a second drain select transistor coupled to the bit line via the first drain select transistor, and wherein a first gate terminal of the first drain select transistor is controllable separately from a second gate terminal of the second drain select transistor.