| 发明名称 |
Integrated Circuit Underfill Scheme |
| 摘要 |
An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression. |
| 申请公布号 |
US2016254169(A1) |
申请公布日期 |
2016.09.01 |
| 申请号 |
US201615152308 |
申请日期 |
2016.05.11 |
| 申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Liang Shih-Wei;Lu Chun-Lin;Wu Kai-Chiang;Yang Ching-Feng;Liu Ming-Kai;Miao Chia-Chun;Wang Yen-Ping |
| 分类号 |
H01L21/56;H01L23/00;H01L23/498;H01L25/065;H01L23/31;H01L21/48;H01L25/00 |
主分类号 |
H01L21/56 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method, comprising:
forming at least two solder bumps over a substrate; forming at least one depression on a top surface of the substrate, the at least one depression extending between the at least two solder bumps; mounting a die over the at least two solder bumps and the substrate; and forming an underfill between the substrate and the die, wherein the at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression. |
| 地址 |
Hsin-Chu TW |
