发明名称 |
BI-DIRECTIONAL PUNCH-THROUGH SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
摘要 |
In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor. |
申请公布号 |
US2016300939(A1) |
申请公布日期 |
2016.10.13 |
申请号 |
US201615088297 |
申请日期 |
2016.04.01 |
申请人 |
Silergy Semiconductor Technology (Hangzhou) LTD |
发明人 |
Yao Fei;Wang Shijun;Qin Bo |
分类号 |
H01L29/74;H01L29/66;H01L29/747 |
主分类号 |
H01L29/74 |
代理机构 |
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代理人 |
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主权项 |
1. A bi-directional punch-through semiconductor device, comprising:
a) a first transistor in a first region of a semiconductor substrate of a first conductivity type, wherein said first transistor comprises a semiconductor buried layer of a second conductivity type in said semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above said semiconductor buried layer, said semiconductor buried layer being configured as a base of said first transistor; and b) a second transistor coupled in parallel with said first transistor, wherein said second transistor is in a second region of said semiconductor substrate of said first conductivity type, wherein said second transistor comprises a second epitaxy region of said epitaxy semiconductor layer above said semiconductor substrate, and a first doped region of said second conductivity type in said second epitaxy region, said first doped region being configured as a base of said second transistor, and wherein said first and second epitaxy regions have different conductivity types. |
地址 |
Hangzhou CN |