| 发明名称 |
SYSTEM ON CHIP POWER MANAGEMENT |
| 摘要 |
An implementation of a system disclosed herein provides an apparatus, comprising a system on chip, wherein the system on chip is configured to receive a sleep command from a host and in response to the sleep command, calculate a primary checksum of a block of data from a low latency memory such as a tightly coupled memory (TCM), copy the primary checksum and the block of data into a volatile storage media, preserve interface variables of the system on chip in the volatile storage media, operate the volatile storage media in a self-refresh mode, and shut down power to other components on the system on chip. |
| 申请公布号 |
US2016224099(A1) |
申请公布日期 |
2016.08.04 |
| 申请号 |
US201514611648 |
申请日期 |
2015.02.02 |
| 申请人 |
Seagate Technology LLC |
发明人 |
Shen Jin Quan;Chng Yong Peng;Zheng Caihua;Tan Choon Kiat |
| 分类号 |
G06F1/32;G06F3/06;G11C11/406 |
主分类号 |
G06F1/32 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a system on chip, wherein the system on chip is configured to receive a sleep command and, in response to the sleep command:
calculate a primary checksum of a block of data from (1) a tightly coupled memory (TCM) or (2) a dynamic random access memory (DRAM),store the primary checksum and the block of data into a volatile storage media,operate the volatile storage media in a self-refresh mode, andshut down power to other components on the system on chip. |
| 地址 |
Cupertino CA US |
