Clock divider circuit with synchronized switching

摘要

The clock divider circuit includes a dividing circuit, a selection circuit, and a synchronization circuit. The dividing circuit is configured to receive an input clock signal at a first frequency, and to produce a number of different periodic signals based thereon. The selection circuit is configured to receive various ones of the periodic signals. An output clock signal may be provided from the selection circuit based on a selection made therein. The input clock signal may have a frequency that is an integer multiple of the output clock frequency. The selection circuit is configured to provide the output clock signal at different, selectable frequencies. The synchronization circuit may control the timing of the switching of the output clock signal from one frequency to the next so that such switching may be performed without glitches.

主权项

1. A circuit comprising:
a dividing circuit coupled to receive an input clock signal and a plurality of divisor select signals, and further configured to generate a plurality of periodic signals including first, second, and third periodic signals; a synchronization circuit coupled to receive a first periodic signal from the dividing circuit, wherein the synchronization circuit is configured to receive input control signals and further configured to generate the divisor select signals responsive to a falling edge of the first periodic signal and a multiplexer select signal responsive to a rising edge of the first periodic signal; and a selection circuit coupled to receive the second and third periodic signals and the multiplexer select signal, wherein the selection circuit is configured to provide an output clock signal based on at least one of the second and third periodic signals and the multiplexer select signal, wherein a frequency of the input clock signal is an integer multiple of a frequency of the output clock signal.