发明名称 |
Decoder architecture systems, apparatus and methods |
摘要 |
An embodiment includes an apparatus that includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.
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申请公布号 |
US2006222000(A1) |
申请公布日期 |
2006.10.05 |
申请号 |
US20050093732 |
申请日期 |
2005.03.30 |
申请人 |
VANNERSON ERIC F;MEHTA KALPESH D;LIPPINCOTT LOUIS A |
发明人 |
VANNERSON ERIC F.;MEHTA KALPESH D.;LIPPINCOTT LOUIS A. |
分类号 |
H04J3/16 |
主分类号 |
H04J3/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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