System and method for automated simulator assertion synthesis and digital equivalence checking

摘要

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

主权项

1. A computer-implemented method comprising:
inputting at least one user-supplied assertion; selectively generating and skewing clocks to convert user-supplied unclocked assertions to clocked assertions for each of a plurality of different verification tools, wherein at least one of the verification tools evaluates analog assertions; generating a stimulus; synthesizing a test bench; using different simulators, for each verification tool, simulating the test bench and capturing simulation results; evaluating result differences between the different verification tools with an assertion status difference engine that compensates for output differences in timing and syntax; and identifying and outputting differences indicating an inconsistency between the different verification tools; wherein the inconsistency is from a verification tool implementation error.