Systems and methods for providing memory controllers with memory access request merging capabilities

摘要

An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.

主权项

1. A method of fulfilling a memory access request with a memory controller operable to communicate with memory, comprising:
receiving the memory access request at a plurality of ports of the memory controller; with the memory controller, identifying which port of the plurality of ports received the memory access request; with the memory controller, identifying whether the memory access request should be merged with a memory access request previously received at the identified port; with the memory controller, issuing a merged memory access request based on the memory access request and the previously received memory access request; with the memory controller, receiving data from the memory that corresponds to the merged memory access request; and with the memory controller, partitioning the received data into a first portion associated with the memory access request and a second portion associated with the previously received memory access request.