CONTROL METHOD AND PROCESSOR SYSTEM WITH PARTITIONED LEVEL-1 INSTRUCTION CACHE

摘要

A processor system having a partitioned level-1 instruction cache and a control method thereof are provided to partition a level-1 instruction cache into plural independent sub caches, activate only one sub cache and inactivate the rest sub caches based on locality of an application program during level-1 instruction cache access, and remove a tag comparison work within the level-1 instruction cache, thereby significantly reducing energy consumed when the level-1 instruction cache is accessed once. Plural level-1 instruction sub caches(230) are independently activated according to an activate signal and independently perform instruction fetch using a virtual address if an instruction request is generated from a processor core(100). A sub cache predictor(210) predicts a level-1 instruction sub cache which will perform the instruction fetch among the plural level-1 instruction sub caches based on previous instruction fetch information according to the generation of the instruction request, and provides the activate signal. A separate buffer(400) for conversion searches an entry among entries, each corresponding to the plural level-1 instruction sub caches, by using the virtual address according to the generation of the instruction request. An instruction output unit(300) compares identification information of the entry searched by the separate buffer for conversion with identification information of the level-1 separate buffer for conversion activated by the activate signal, and transmits an instruction, fetched in the activated level-1 separate buffer for conversion, to the processor core when the comparison request is matched with setup conditions.