New FIFO memory structure and operting procedure of such a memory

摘要

The memory has a synchronous RAM (SRAM) (110) with a frequency half of that of the memory and storing simultaneously two words of n-bits received successively on an input (DIN) of the memory. A storage circuit (130) stores a word of n-bits received on the input (DIN) or simultaneously two words of n-bits received from the SRAM. The circuit generates one word at the output of the memory. An independent claim is also included for a process of controlling contents of a first-in first-out memory.