发明名称 |
FREQUENCY SYNTHESIZER OUTPUT CYCLE COUNTER INCLUDING RING ENCODER |
摘要 |
A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output. |
申请公布号 |
US2016187401(A1) |
申请公布日期 |
2016.06.30 |
申请号 |
US201414588014 |
申请日期 |
2014.12.31 |
申请人 |
Texas Instruments Incorporated |
发明人 |
ALTUS TOM;SUBBURAJ KARTHIK;SAMALA SREEKIRAN;GANESAN RAGHU |
分类号 |
G01R23/02 |
主分类号 |
G01R23/02 |
代理机构 |
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代理人 |
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主权项 |
1. A method of frequency estimation, comprising:
receiving a clock output from a frequency synthesizer at an input of a ring encoder which comprises a plurality of series connected flip flops and at least one inverter connected cyclically in a ring format; said ring encoder generating a divided down version of said clock output (ring encoder output clock) and an encoded output which represents least significant bits (LSBs) of a clock cycle count of said clock output; running a binary counter using said ring encoder output clock, wherein said binary counter provides an output count which represents most significant bits (MSBs) of said clock cycle count; using a reference clock, sampling said encoded output to provide a sampled encoded output and sampling said output count to provide a sampled output count; error correcting said sampled encoded output to provide a corrected sampled encoded output; combining said corrected sampled encoded output and said sampled output count to provide a combined output, and using said combined output, estimating an instantaneous or average frequency of said clock output to provide an estimated clock frequency. |
地址 |
Dallas TX US |