| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a vernier and its forming method which is effective to prevent errors in the overlay accuracy measurement and to reduce the number of process steps by forming trenches of paddle type in a region where the vernier is formed. <P>SOLUTION: The method for forming the overlay accuracy measurement vernier includes a step of forming a first vernier pattern in a predetermined region on a semiconductor substrate, a step of forming a trench of first depth by etching by using the first vernier pattern as a mask, a step of forming a second vernier pattern of width larger than that of the first vernier pattern so that the first vernier pattern may be included, a step of performing an etching process by using the second vernier pattern as a mask and forming a trench of second depth having different levels of predetermined width, a step of forming an insulating film so that the trenches may be embedded after eliminating the first vernier pattern and the second vernier pattern and a step of etching the insulating film so that the semiconductor substrate in the vernier region may be exposed. <P>COPYRIGHT: (C)2007,JPO&INPIT |
