| 摘要 |
PROBLEM TO BE SOLVED: To obtain a delay circuit which can produce an output signal with a desired delay amount of time even if pulse width of the input signal is short. SOLUTION: The delay circuit includes a first flip-flop to which an input signal is input from the set input, a first inverter which inverts an input signal, a second flip-flop to which an output signal from the first inverter is input from the set input, a first delay generating circuit which inputs an output signal from the first flip-flop to make the input signal delay and outputs the signal delayed to the reset input of the first flip-plop, a second delay generating circuit which inputs an output signal from the second flip-flop to make the input signal delay and outputs the signal delayed to the reset input of the second flip-plop, and a third flip-flop which inputs an output signal from the first delay generating circuit from the set input. Then, the first and second delay generating circuits perform a delaying operation in response to charging to a capacitor. COPYRIGHT: (C)2008,JPO&INPIT
|
