SHIFT REGISTER, DISPLAY DRIVER AND DISPLAY

摘要

A shift register comprises a plurality of stages (62) which are activated in sequence. Each stage comprises a logic circuit (44) controlling first and second output circuits. The first output circuit comprises a first switch in the form of a transistor (56), which connects an output (GL) of the stage (62) to receive a pulse width control (PWC) signal when the stage is active. A second switch in the form of a transistor (58) connects the stage output (GL) to receive an inactive signal level when the stage (62) is inactive. The second output circuit comprises a third switch in the form of a transistor (60), which connects a further output (OUT) to receive an active signal level when the stage (62) is active. A fourth switch in the form of a transistor (62) connects the further output (OUT) to receive an inactive signal level when the stage (62) is inactive. The further output (OUT) of each stage is connected to the logic circuit (44) of at least one adjacent stage, such as a reset input of a preceding stage and/or a set input of a succeeding stage.