| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated device which can operate in the state that both 0-read and 1-read are hard to delay. <P>SOLUTION: The regulator circuit 100 inputs the address transition detect signals (ATD) and adjusts the pulse width of the signals ATDEQ 32 to output following the level variations of the voltages Vp and Vn supplied from the voltage Vp generator circuit 142 and the voltage Vn generator circuit 132, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
