| 摘要 |
PROBLEM TO BE SOLVED: To improve resolution of an integral A-D converter without increasing a clock frequency. SOLUTION: A trigger signal is generated which is a comparison output of a comparator 11 at a timing of polarity inversion. A clock signal from a phase locked-loop circuit 13 is supplied to a counter 12, and its counting is stopped by the trigger signal. A ring oscillator 34 provided in the phase locked-loop circuit 13 is configured by, for example, differential delay elements 41-44 connected in cascade, and tap signals of respective steps are each supplied to a latch circuit 15 via buffers 14a-14d. The signals supplied to the latch circuit 15 are held by the trigger signal. The signal held in the latch circuit 15 are supplied to a decoding circuit 16, and the supplied signals are converted into numeric values in accordance with the patterns of signals. The numeric values converted in the decoding circuit 16 are added to the lowest order of the counted value of the counter 12 and taken out into an output line 17. COPYRIGHT: (C)2008,JPO&INPIT
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