发明名称 METHOD FOR VOID REDUCTION IN SOLDER JOINTS
摘要 The invention relates to a method for the soldering connection at least of one electronic component (104, 204, 304, 404, 504) to a carrier plate (100, 200, 300, 400, 500), wherein the carrier plate has at least one carrier plate contact surface (102, 202, 302, 402, 502) and the at least one electronic component has at least one corresponding component contact surface (105), wherein the at least one carrier plate contact surface is surrounded by a solder resist layer (101, 201, 301, 401, 401) that abuts the at least one carrier plate contact surface, wherein the method comprises the following steps: a) applying, at least in sections, solder paste (106, 206, 306, 406, 506) to the solder resist layer (101, 201, 301, 401, 501) and with minimal overlapping with the carrier plate contact surface (102, 202, 302, 402, 502) abutting the solder resist layer; b) providing the carrier plate with the at least one electronic component (104, 204, 304, 404, 504), wherein the at least one component contact surface (105) at least partially covers the corresponding at least one carrier plate contact surface (102, 202, 302, 402, 502); and c) heating the solder paste (106, 206, 306, 406, 506) to produce a soldered connection between the carrier plate and the at least one component.
申请公布号 WO2016094915(A1) 申请公布日期 2016.06.23
申请号 WO2015AT50295 申请日期 2015.11.18
申请人 ZIZALA LICHTSYSTEME GMBH 发明人 EDLINGER, ERIK
分类号 B23K1/00;H05K1/11;H05K3/30;H05K3/34 主分类号 B23K1/00
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