METHOD FOR MANUFACTURING HIGH VOLTAGE LED FLIP CHIP

摘要

A method for manufacturing a high voltage LED flip chip is provided, including: providing a substrate; forming an epitaxy stacking layer on the substrate; etching the epitaxy stacking layer to form a first groove and a Mesa-platform on each chip-unit region; forming a first electrode on each of the Mesa-platforms, wherein the first electrodes on two neighboring chip-unit regions form a second groove; forming a first insulation layer covering the Mesa-platforms and the first electrodes, filling the second groove and partially filling the first grooves to form a third groove; etching the first insulation layer to form fourth groove; and forming an interconnection electrode, wherein the interconnection electrode fills the third groove and the fourth groove, two neighboring interconnection electrodes form a fifth groove, the interconnection electrode connects the first electrode on one chip-unit region and the first semiconductor layer on the other chip-unit region. LED formed has improved performance.

主权项

1. A method for manufacturing a high voltage LED flip chip, comprising:
providing a substrate, wherein the substrate comprises two or more regions, and the two or more regions comprise a first region where an upper electrode is to be formed and a second region where a lower electrode is to be formed; forming an epitaxy stacking layer on the substrate, wherein the epitaxy stacking layer comprises a first semiconductor layer, a second semiconductor layer and a quantum well layer between the first semiconductor layer and the second semiconductor layer; etching the epitaxy stacking layer to form at least one first groove in each of the two or more regions, wherein the first groove exposes the first semiconductor layer, and a remaining portion of the epitaxy stacking layer on each of the two or more regions forms a Mesa-platform; forming a first electrode on each of the Mesa-platforms, wherein an area between the first electrodes in two adjacent regions forms a second groove; forming a first insulation layer, wherein the first insulation layer covers the Mesa-platforms and the first electrodes, and the first insulation layer fills the second groove and fills the first grooves; etching the first insulation layer to form a third groove between two adjacent Mesa-platforms and at least one fourth groove in each of the two or more regions, wherein the third groove exposes a surface of the first semiconductor layer, and the at least one fourth groove exposes a surface of the first electrode; and forming an interconnection electrode, wherein the interconnection electrode comprises a first portion connecting the first semiconductor layer through the third groove in a particular region with the first electrode through the fourth groove in another region adjacent to the particular region.