发明名称 TEST DEVICE, TEST METHOD, TEST PROGRAM, FPGA AND CPLD
摘要 PROBLEM TO BE SOLVED: To execute a connection test of channel device (CH) and peripheral processor (PCU) without using an expensive pseudo input and output processor (PIO) while improving the test efficiency and the coverage. SOLUTION: This test device comprises a CH function achievement part achieving CH function and a CPU function achievement part achieving PCU function. (1) The CH function achievement part is operated in a non-test mode, and (2) when a switching instruction to a test mode is received, the CPU function achievement part is operated instead of the CH function achievement part. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008090776(A) 申请公布日期 2008.04.17
申请号 JP20060273724 申请日期 2006.10.05
申请人 NEC CORP 发明人 MIYAZAKI GEN
分类号 G06F13/00 主分类号 G06F13/00
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