发明名称 |
Semiconductor integrated circuit device |
摘要 |
Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
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申请公布号 |
US2005040538(A1) |
申请公布日期 |
2005.02.24 |
申请号 |
US20040956159 |
申请日期 |
2004.10.04 |
申请人 |
KOUBUCHI YASUSHI;NAGASAWA KOICHI;MONIWA MASAHIRO;YAMADA YOUHEI;TAKEDA TOSHIFUMI |
发明人 |
KOUBUCHI YASUSHI;NAGASAWA KOICHI;MONIWA MASAHIRO;YAMADA YOUHEI;TAKEDA TOSHIFUMI |
分类号 |
H01L21/76;H01L21/304;H01L21/3205;H01L21/768;H01L21/8242;H01L23/00;H01L27/108;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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