| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide similar tools to speed communication that have traditionally been used to speed computation by minimizing communication delay between processors in a multiprocessor environment to bring to a multiprocessor what vectorization brought to a single processor, namely, the capability to program optimal communication algorithms on an architecture that can enhance their performance in terms of wall clock time. <P>SOLUTION: In addition to the usual complement of a logic operation unit and an arithmetic unit, each processor contains a programmable communication unit that orchestrates traffic between a network and registers that communicate directly with comparable registers in neighboring processors. Communication tasks are performed out of these registers like computational tasks on a vector uniprocessor. The architecture is balanced and the hardware/software combination is scalable to any number of processors. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
